The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally doped monocrystalline silicon, and a plurality of interleaved dielectric and conductive layers formed thereon. In a conventional semiconductor device 100 illustrated in FIG. 1, substrate 1 is provided with field oxide 2 for isolating an active region comprising source/drain regions 3, and a gate electrode 4, typically of doped polysilicon, above the semiconductor substrate with gate oxide 5 therebetween. Interlayer dielectric layer 6, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer 8, and source/drain regions 3 through contacts 7, and to transistor gate electrode 49. Dielectric layer 9, typically silicon dioxide, is deposited on conductive layer 8, and another conductive layer 10, typically aluminum or an aluminum-base alloy, formed on dielectric layer 9 and electrically connected to conductive layer 8 through vias 11.
With continued reference to FIG. 1, conductive layer 10 is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer 12, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer 13 deposited thereon. Protective dielectric layer 13 typically comprises a nitride layer, such as silicon nitride (Si.sub.3 N.sub.4). Alternatively, protective dielectric layer 13 may comprise a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer 13 provides scratch protection to the semiconductor device and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer 13, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer 10 for external connection by means of bonding pad 14 and electrically conductive wires 15 or an external connection electrode (not shown).
Although only two conductive layers 8 and 10 are depicted in FIG. 1 for illustrative convenience, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements, e.g., five conductive metal layers. Also in the interest of illustrative convenience, FIG. 1 does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continually shrink in size, it becomes necessary to decrease the depth of the source and drain regions in the semiconductor substrate, i.e., the junction depth. For example, in forming a polycrystalline silicon gate electrode having a width of about 0.25 microns, the junction depth (X.sub.J) should be no greater than about 800 .ANG.. This objective is extremely difficult to achieve, particularly when implanting impurities to dope the gate electrode and form source/drain regions.
For example, conventional semiconductor methodology comprises doping polysilicon gate electrode 4 and forming source/drain regions 3 in the same ion implantation. That is, the ion implantation to form source/drain regions 3 also functions to dope polysilicon gate electrode 4. However, in order to achieve shallow source/drain junctions, the implantation energy for forming source/drain regions 3 is relatively low. The implanted impurities achieve desirably shallow penetration in substrate 1 at the expense of shallow penetration in gate electrode 4. This causes gate depletion, i.e., lack of carriers at the gate electrode/gate oxide interface, resulting in decreased capacitance and reduced drive current.
Ion implantation can be performed at higher energy levels to reduce gate depletion. However, after activation annealing, the resulting source/drain regions extend considerably beyond the targeted maximum X.sub.J of about 800 .ANG.. An undesirably deep Xi can cause short channel effects, generating a leakage current which degrades the performance of the semiconductor device.